Boot Sequence:
BIOS/UEFI POST initiates
Bootloader (GRUB/LILO) loads kernel
Transition from real mode to protected mode
CR0.PE bit set, enabling segmentation
Memory Management:
Global Descriptor Table (GDT) defines segments
CR3 sets Page Directory Base Register (PDBR)
Multi-level paging: PML4, PDPT, PD, PT
TLB caches recent translations
Page Fault Handler (#PF) manages access violations
Interrupt Handling:
Interrupt Descriptor Table (IDT) vectors exceptions/IRQs
8259 PIC for legacy interrupt routing
Advanced Programmable Interrupt Controller (APIC)
Local APIC timer for per-CPU interrupts
I/O APIC for multi-processor interrupt routing
Process Management:
Task State Segment (TSS) for context data
Scheduler implements priority-based algorithms
e.g., Completely Fair Scheduler (CFS)
Synchronization: semaphores, mutexes, RCU, futexes
System Calls:
SYSCALL/SYSENTER instructions for fast kernel transition
System call number in RAX register
SWAPGS swaps user/kernel GS base
Security Features:
KASLR randomizes kernel load address
KPTI separates user/kernel pages
SecureBoot verifies bootloader integrity
TPM measures boot sequence
Virtualization:
Virtual Machine Control Structure (VMCS)
Extended Page Tables (EPT) for nested paging
VMX non-root operation for guest code execution
VMFUNC for fast EPT switching
I/O and Device Management:
DMA controllers for CPU-independent transfers
Programmed I/O (PIO) and Memory-Mapped I/O (MMIO)
IOMMU (Intel VT-d/AMD-Vi) for DMA remapping
SR-IOV for PCIe device virtualization
Cache Coherence:
MESI/MESIF protocols maintain multi-core consistency
MTRR and PAT configure memory types
CLFLUSH/CLFLUSHOPT for explicit cache line flushing
System Configuration:
ACPI tables (DSDT, SSDT) define hardware setup
_OSI method for OS-specific optimizations
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